The present invention relates generally to high frequency clock divider circuits, and more particularly to a high frequency clock divider circuit which can be used to divide the voltage controlled oscillator (VCO) output clock and feed the divided output clock back to the phase detector in a phase locked loop (PLL) circuit.
High frequency PLL circuits that operate at frequencies above 1 GHz are widely used in digital radio, communications and multimedia applications and the like. Typical PLL designs include a phase comparator, a PLL clock divider, and a VCO. The PLL clock divider divides the VCO output clock to provide feedback to an input of the phase comparator. Programmable PLL clock dividers having fine frequency steps are needed to maximize the granularity of the PLL output clock frequency steps, i.e., are needed to minimize the difference that can be provided between two consecutive PLL output clock frequency steps.
FIG. 1 shows a conventional PLL including a phase detector 2 which receives a clock input signal REFCLK, and also receives a divided-down clock feedback signal CLK on conductor 13. The output 3 of phase detector 2 is connected to the input of a conventional charge pump circuit 4, the output 5 of which is connected to the input of a conventional voltage controlled oscillator (VCO) 8. The output CLK of VCO 9 is connected to the input of a conventional clock divider 10, the output of which generates the above mentioned divided-down clock signal on conductor 13. Clock divider 10 receives a N-bit input signal which determines the divide ratio DIV_RATIO of clock divider 10. For example, the user may require various divide ratio values in order to select various channels of a digital radio. The divide ratio is generated by a divide ratio generator 11.
The closest prior art is believed to include the technical article “A 2 GHz Programmable Counter with New Re-Loadable D Flip-Flop” by Do, M. A., Yu, X. P., Ma, J. G., Yeo, K. S., Wu, R., Zhang, Q. X. in Electron Devices and Solid-State Circuits, 2003 IEEE Conference on 16-18 Dec. 2003, Pages 269-272 (Digital Object Identifier 10.1109/EDSSC.2003.1283529). This reference discloses a high-speed programmable counter with a new reloadable D Flip-flop which integrates the programmable function to a single true-single-phase-clock (TSPC) D flip-flop. The technical article “A CMOS High-Speed Wide-Range Programmable Counter” by Sang-Hoon Lee and Hong June Park, in Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions, Volume 49, Issue 9, September 2002, Page(s):638-642 (Digital Object Identifier 10.1109/TCSII.2002.805627), discloses a CMOS high speed wide-range programmable divide-by-N counter. The technical article “A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider” by Baoyong Chi, Xueyi Yu, Woogeun Rhee and Zhihua Wang in Circuits and Systems, 2007, ISCAS 2007, IEEE International Symposium on 27-30 May 2007, Pages 3051-3054 (Digital Object Identifier 10.1109/ISCAS.2007.378052) discloses an architecture of a fractional-N phase-locked loop for digital clock generation, in which the divide ratio generator is implemented by means of a delta-sigma modulator and the clock divider is implemented by means of shift register circuitry and flip-flops.
Providing a dynamic divide ratio in a clock divider as shown in Prior Art FIG. 1 is known, but requires use of “special” logic circuit designs. For example, the above mentioned article “A 2 GHz Programmable Counter with New Re-Loadable D Flip-Flop” discloses a high-speed programmable counter, but it is not implemented using standard library logic circuit cells. A shortcoming of implementing any of the prior art clock divider designs (such as those disclosed in the foregoing technical articles) using such standard library cells is that the speed limitations of known standard library cells at the current state of the art makes it impossible to achieve reliable division of clock signals having frequencies in excess of roughly 1 GHz. The prior art clock divider designs necessarily use circuits which have been optimized for speed and therefore have not been optimized for use in standard cell integrated circuit layouts or topography.
A problem with the prior art PLL clock divider circuits is that only special logic circuitry that is custom designed and optimized for high frequency operation is capable of accurately dividing the VCO output clock signal at VCO output clock frequencies higher than roughly 1 GHz. Another problem of the prior art clock divider circuits is that it has been difficult to implement them with “fine programming steps” for frequencies higher than roughly 1 GHz. Another problem of the prior art clock divider circuits is that clock jitter introduced by them has been greater than the needed low level of clock jitter, which is as low as a few pico-seconds for some PLL applications.
Some of the known clock dividers are based on high speed custom-designed logic circuits, and other known clock dividers are based on standard library logic circuit cells. The known clock dividers based on standard library cells are not capable of operating at sufficiently high frequencies to be useful in high speed PLL circuits that operate at frequencies above roughly 500 MHz to 1 GHz. At the present state of the art, it would be very desirable in some applications to have a 6-bit (for example) programmable counter, which nevertheless is constructed of logic circuit cells from a standard CMOS cell library and which is capable of operating at 1.5 GHz. However, no presently available 6-bit programmable counter constructed of cells from any typical standard cell CMOS library can operate at more than roughly 500 MHz to 1 GHz.
So-called standard library logic cells are inadequate for use in a programmable high-speed clock divider capable of operating at frequencies above roughly 500 MHz to 1 GHz because such standard library logic cells are not capable of operating reliably at frequencies above roughly 500 MHz to 1 GHz, whereas in applications to which the subsequently described invention is directed, the logic gates need to have gate delays of less than 1 nanosecond.
It should be appreciated that the topographies of individual standard library cells ordinarily are optimized primarily for easy layout and easy use by conventional automatic integrated circuit design tools. This usually results in standard cells not being optimized for high speed operation. Therefore, logic circuits which are implemented using standard cells generally have limited operating speed. If high speed circuit operation is required, standard library cells generally can not be used, and instead a time consuming and costly “custom” layout is required.
Libraries of so-called standard logic cells usually include logic gate cells and flip-flop cells. A characteristic of typical standard library cells is that they all have the same height, although they may have different widths. The individual logic cells also have well defined input and output connection point locations and well-defined power connection point locations, in order to allow rapid, automatic routing of interconnect conductors between connection points of various cells in rows of standard cells. Such standard logic circuit cells therefore may be readily and rapidly arranged side-by-side as “tiles” in an integrated circuit chip layout. Consequently, the topography of the logic circuit on a chip can be quickly and readily designed using standard logic circuit cells. In contrast, both the circuit design and the design of the integrated circuit layout of the above mentioned high speed, custom-designed logic circuits usually is time-consuming and costly.
As a practical matter, it would be difficult at the present state-of-the-art to design library cells which would be fast enough to meet the previously mentioned 1 nanosecond time requirements that would need to be met in order to provide a programmable 1.5 GHz clock divider. Consequently, if the above mentioned prior art clock dividers are to be programmable, e.g., are to have dynamic divide ratios, it would be necessary to provide costly, time-consuming custom integrated circuit designs and costly, time-consuming chip layouts.
Thus, there is an unmet need for a practical, economical clock divider circuit that is capable of accurately dividing clock frequencies, such as VCO output clock frequencies, without using special, complex extraordinarily high-speed logic circuitry.
There also is an unmet need for a practical, economical clock divider circuit capable of dividing signals of frequencies higher than roughly 500 MHz to 1 GHz which can, as a practical matter, be implemented using standard integrated circuit library cells, without substantial use of custom chip layout procedures.
There also is an unmet need for a practical, economical clock divider circuit capable of dividing signals of frequencies higher than roughly 500 MHz to 1 GHz in “fine programming steps” which can, as a practical matter, be implemented using standard integrated circuit library cells without substantial use of custom chip layout procedures.
There also is an unmet need for a practical, economical clock divider circuit capable of dividing signals of frequencies higher than roughly 500 MHz to 1 GHz with a low amount of clock jitter, of the order of a few pico-seconds, to provide an output clock, e.g., a PLL output clock, that is sufficiently stable for most applications.
There also is an unmet need for a practical, economical clock divider circuit capable of dividing signals of frequencies higher than roughly 500 MHz to 1 GHz which is capable of dividing by both static and dynamic dividing values.